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19-0119; Rev. 1; 12/93
ual Man et Kit She ion uat s Data l Eva llow Fo
+3V, 8-Bit ADC with 1A Power-Down
___________________________Features
o Single +3.0V to +3.6V Supply o 1.8s Conversion Time o Power-Up in 900ns o Internal Track/Hold o 400ksps Throughput o Low Power: 1.5mA (Operating Mode) 1A (Power-Down Mode) o 300kHz Full-Power Bandwidth o 20-Pin DIP, SO and SSOP Packages o No External Clock Required o Unipolar/Bipolar Inputs o Ratiometric Reference Inputs o 2.7V Version Available - Contact Factory
_______________General Description
The MAX152 high-speed, microprocessor (P)-compatible, 8-bit analog-to-digital converter (ADC) uses a half-flash technique to achieve a 1.8s conversion time, and digitizes at a rate of 400k samples per second (ksps). It operates with single +3V or dual 3V supplies and accepts either unipolar or bipolar inputs. - ---- -- ---- -- ---- - A P O W E R D O W N pin reduces current consumption to a typical value of 1A. The part returns from powerdown and acquires an input signal in less than 900ns, providing large reductions in supply current in applications with burst-mode input signals. The MAX152 is DC and dynamically tested. Its P interface appears as a memory location or input/output port that requires no external interface logic. The data outputs use latched, three-state buffered circuitry for direct connection to a P data bus or system input port. The ADC's input/reference arrangement enables ratiometric operation. A fullyassembled evaluation kit provides a proven PC board layout to speed prototyping and design.
MAX152
______________Ordering Information
PART MAX152CPP MAX152CWP MAX152CAP MAX152C/D MAX152EPP MAX152EWP MAX152EAP TEMP. RANGE 0C to +70C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 20 Plastic DIP 20 Wide SO 20 SSOP Dice* 20 Plastic DIP 20 Wide SO 20 SSOP
_______________________Applications
Cellular Telephones Portable Radios Battery-Powered Systems Burst-Mode Data Acquisition Digital Signal Processing Telecommunications High-Speed Servo Loops
20 CERDIP** MAX152MJP -55C to +125C * Contact factory for dice specifications. ** Contact factory for availability and processing to MIL-STD-883.
________________Functional Diagram
VDD 12 VREF+ 11 VREFVIN 1 20 18
4-BIT FLASH ADC
__________________Pin Configuration
TOP VIEW
VIN
PWRDN
1 2 3 4 5 6 7 8 9
20 19 18 17
VDD VSS PWRDN D7 (MSB) D6 D5 D4 CS VREF+ VREF-
D0 (LSB) D1 THREESTATE DRIVERS D0-D7 DATA OUT PINS 2-5, 14-17 D2 D3 WR/RDY MODE RD INT
4-BIT DAC VREF+ 16 4-BIT FLASH ADC (4LSB) TIMING AND CONTROL CIRCUITRY 6 7 10 13 8 GND MODE WR/RDY CS RD
MAX152
16 15 14 13 12 11
MAX152
GND 10
19 9 INT VSS
DIP/SO/SSOP 1
________________________________________________________________ Maxim Integrated Products
Call toll free 1-800-998-8800 for free samples or literature.
+3V, 8-Bit ADC with 1A Power-Down MAX152
ABSOLUTE MAXIMUM RATINGS
VDD to GND .............................................................-0.3V to +7V VSS to GND ..............................................................+0.3V to -7V Digital Input Voltage to GND ........................-0.3V, (VDD + 0.3V) Digital Output Voltage to GND .....................-0.3V, (VDD + 0.3V) VREF+ to GND................................(VSS - 0.3V) to (VDD + 0.3V) VREF- to GND.................................(VSS - 0.3V) to (VDD + 0.3V) VIN to GND .....................................(VSS - 0.3V) to (VDD + 0.3V) Continuous Power Dissipation (TA = +70C) Plastic DIP (derate 11.11mW/C above +70C) ..........889mW Wide SO (derate 10.00mW/C above +70C)..............800mW SSOP (derate 8.00mW/C above +70C) ....................640mW CERDIP (derate 11.11mW/C above +70C) ...............889mW Operating Temperature Ranges: MAX152C__ ........................................................0C to +70C MAX152E__ .....................................................-40C to +85C MAX152MJP ..................................................-55C to +125C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Unipolar input range, VDD = 3.0V to 3.6V, GND = 0V, VSS = GND, VREF+ = 3.0V, VREF- = GND, specifications are given for RD mode (pin 7 = GND), TA = TMIN to TMAX, unless otherwise noted.) PARAMETER ACCURACY (Note 1) Resolution Total Unadjusted Error Differential Nonlinearity Zero-Code Error (Note 2) Full-Scale Error (Note 2) DYNAMIC PERFORMANCE (Note 3) Signal-to-Noise Plus Distortion Ratio MAX152C/E, fSAMPLE = 400kHz, fIN = 30.273kHz MAX152M, fSAMPLE = 340kHz, fIN = 30.725kHz MAX152C/E, fSAMPLE = 400kHz, fIN = 30.273kHz MAX152M, fSAMPLE = 340kHz, fIN = 30.725kHz MAX152C/E, fSAMPLE = 400kHz, fIN = 30.273kHz MAX152M, fSAMPLE = 340kHz, fIN = 30.725kHz VIN = 3.0Vp-p 0.28 VIN IIN CIN RREF 1 VREFVSS VSS < VIN < VDD 22 2 4 VDD VREF+ VREF50 dB 50 0.3 0.5 VREF+ 3 MHz V/s V A pF k V V 45 dB 45 -50 dB -50 N TUE DNL Unipolar range No-missing-codes guaranteed Unipolar and bipolar modes Unipolar and bipolar modes 8 1 1 1 1 Bits LSB LSB LSB LSB SYMBOL CONDITIONS MIN TYP MAX UNITS
S/(N+D)
Total Harmonic Distortion
THD
Spurious-Free Dynamic Range
Input Full-Power Bandwidth Maximum Input Slew Rate, Tracking ANALOG INPUT Input Voltage Range Input Leakage Current Input Capacitance REFERENCE INPUT Reference Resistance VREF+ Input Voltage Range VREF- Input Voltage Range 2
_______________________________________________________________________________________
+3V, 8-Bit ADC with 1A Power-Down
ELECTRICAL CHARACTERISTICS (continued)
(Unipolar input range, VDD = 3.0V to 3.6V, GND = 0V, VSS = GND, VREF+ = 3.0V, VREF- = GND, specifications are given for RD mode (pin 7 = GND), TA = TMIN to TMAX, unless otherwise noted.) PARAMETER LOGIC INPUTS Input High Voltage Input Low Voltage VINH VINL CS, WR, RD, PWRDN MODE CS, WR, RD, PWRDN MODE CS, RD, PWRDN Input High Current Input Low Current Input Capacitance (Note 4) LOGIC OUTPUTS INT, D0-D7, ISINK = 20A Output Low Voltage VOL INT, D0-D7, ISINK = 400A RDY, ISINK = 1mA Output High Voltage Floating-State Current Floating Capacitance (Note 4) POWER REQUIREMENTS Positive Supply Voltage Negative Supply Voltage VDD VSS Unipolar operation Bipolar operation (Note 2) MAX152C, CS = RD = 0, PWRDN = VDD MAX152E/M, CS = RD = 0, PWRDN = VDD MAX152C, CS = RD = 0, PWRDN = VDD MAX152E/M, CS = RD = 0, PWRDN = VDD MAX152C/E/M -3.6 2.5 2.5 1.5 1.5 1 1 1 1/16 3.0 GND -3.0 5 6 mA 3 3.5 50 50 25 1/4 A A A LSB 3.6 V V VOH ILKG COUT INT, D0-D7, ISOURCE = 20A INT, D0-D7, ISOURCE = 400A D0-D7, RDY D0-D7, RDY 5 VDD-0.1 VDD-0.4 3 8 0.1 0.4 0.4 V A pF V IINH IINL CIN WR MODE CS, WR, RD, PWRDN, MODE CS, WR, RD, PWRDN, MODE 5 15 2.0 2.4 0.66 0.8 1 3 100 1 8 A pF A V V SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX152
VDD = 3.6V Positive Supply Current IDD VDD = 3.0V
Power-Down VDD Current (Note 5) Negative Supply Current Power-Down VSS Current Power-Supply Rejection PSR ISS
CS = RD = VDD, PWRDN = 0
CS = RD = 0, PWRDN = VDD CS = RD = VDD, PWRDN = 0 VDD = 3.3V 10%
Note 1: Accuracy measurements performed at VDD = 3.0V, unipolar mode. Operation over supply range is guaranteed by powersupply rejection test. Note 2: Bipolar tests are performed with VREF+ = +1.5V, VREF- = -1.5V, VSS = -3.0V. Note 3: Unipolar input range, VIN = 3.0VP-P, WR-RD mode, VDD = 3.0V Note 4: Guaranteed by design. Note 5: Power-down current increases if control inputs are not driven to ground or VDD. _______________________________________________________________________________________ 3
+3V, 8-Bit ADC with 1A Power-Down MAX152
TIMING CHARACTERISTICS
(Unipolar input range, VDD = 3V, VSS = 0V, TA = +25C, unless otherwise noted.) (Note 6) PARAMETER Conversion Time (WR-RD Mode) Conversion Time (RD Mode) Power-Up Time CS to RD,WR Setup Time CS to RD,WR Hold Time CS to RDY Delay Data Access Time (RD Mode) (Note 7) RD to INT Delay (RD Mode) Data Hold Time (Note 8) Delay Time Between Conversions WR Pulse Width Delay Time Between WR and RD Pulses RD Pulse Width Data Access Time (Note 7) RD to INT Delay WR to INT Delay RD Pulse Width SYMBOL tCWR tCRD tUP tCSS tCSH tRDY tACC0 tINTH tDH tP tWR tRD tREAD1 WR-RD mode, determined by tACC1 (Figure 6) WR-RD mode, tRD < tINTL, CL = 100pF (Figure 6) CL = 50pF WR-RD mode, tRD > tINTL, determined by tACC2 (Figure 5) WR-RD mode, tRD < tINTL , CL = 100pF (Figure 5) Stand-alone mode, CL = 50pF Stand-alone mode, CL = 100pF 180 0.7 450 0.6 0.8 400 10 CL = 50pF, RL = 5.1k to VDD CL = 100pF CL = 50pF 100 0 0 100 tCRD +100 160 100 600 0.66 0.9 500 10 CONDITIONS tRD < tINTL, CL = 100pF ALL GRADES TA = +25C MIN TYP MAX 1.8 2.0 0.9 0 0 120 tCRD +130 170 130 700 0.8 1.0 600 10 MAX152C/E TA = TMIN to TMAX MIN MAX 2.06 2.3 1.2 0 0 140 tCRD +150 180 150 MAX152M TA = TMIN to TMAX MIN MAX 2.4 2.6 1.4 UNITS s s s ns ns ns ns ns ns ns s s ns
tACC1 tRI tINTL tREAD2
400 300 1.45 220
500 340 1.6 250
600 400 1.8
ns ns s ns
Data Access Time (Note 7) WR to INT Delay Data Access Time After INT (Note 7)
tACC2 tIHWR tID
180 180 100
220 200 130
250 240 150
ns ns ns
Note 6: Input control signals are specified with tr = tf = 5ns, 10% to 90% of +3.0V, and timed from a voltage level of 1.3V. Timing delays get shorter at higher supply voltages. See the Converson Time vs. Supply Voltage graph in the Typical Operating Characteristics to extrapolate timing delays at other power-supply voltages. Note 7: See Figure 1 for load circuit. Parameter defined as the time required for the output to cross 0.66V or 2.0V. Note 8: See Figure 2 for load circuit. Parameter defined as the time required for the data lines to change 0.5V.
4 _________________________________________________________________________________________ _______________________________________________________________________________________
+3V, 8-Bit ADC with 1A Power-Down
__________________________________________Typical Operating Characteristics
(TA=+25C, unless otherwise noted).
CONVERSION TIME vs. AMBIENT TEMPERATURE
tCRD (NORMALIZED TO VALUE AT +25C) 1.6 1.4 1.2 VDD = 3.6V 1.0 0.8 -80 0.6 0.4 -60 -20 20 60 100 140 TEMPERATURE (C) VDD = 3.0V -100 -120 0 40 80 120 160 200 FREQUENCY (kHz) VDD = 3.3V 0 -20 RATIO (dB) -40 -60 fIN = 30.27 kHz fSAMPLE = 400ksps SNR = 48.2dB EFFECTIVE BITS
MAX152
SIGNAL-TO-NOISE RATIO
8.0 7.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 1k
EFFECTIVE BITS vs. INPUT FREQUENCY, WR-RD MODE
VDD = 3.0V fSAMPLE = 400kHz VIN = 2.98Vp-p TA = TMIN to TMAX 10k 100k 1M
INPUT FREQUENCY (Hz)
CONVERSION TIME vs. SUPPLY VOLTAGE
TIMING (NORMALIZED TO VDD = 3.0V) 1400 1300 1200 tCRD (ns) 1100 1000 900 800 2.8 3.0 3.2 3.4 3.6 3.8 4.0 SUPPLY VOLTAGE (V) 1.1
NORMALIZED TIMING vs. SUPPLY VOLTAGE
10,000
AVERAGE POWER CONSUMPTION vs. CONVERSION RATE USING PWRDN
VDD = 3.0V SUPPLY CURRENT (A) 1000
1.0
0.9 0.8
100
10
0.7 1 2.8 3.0 3.2 3.4 3.6 3.8 4.0 1 10 100 1k 10k 100k 1M SUPPLY VOLTAGE (V) CONVERSIONS/SEC
SUPPLY CURRENT vs. SUPPLY VOLTAGE
6 CS = RD = 0V SUPPLY CURRENT (mA) 5 MILITARY EXTENDED ERROR (LSBs) 4 5
ERROR vs. POWER-UP TIME
MAX186-5
VDD = 3.0V
4
3
3 COMMERCIAL 2 +25C 1 2.8 3.0 3.2 3.4 3.6 3.8 SUPPLY VOLTAGE (V)
2
1
VDD = 3.6V
0 120 160 200 240 280 320 tUP (ns)
_________________________________________________________________________________________________
5
+3V, 8-Bit ADC with 1A Power-Down MAX152
VDD VDD 3k DATA OUTPUTS DATA OUTPUTS DATA OUTPUTS DATA OUTPUTS
3k
3k
CL
CL
3k
10pF
10pF
A. HIGH-Z TO VOH
B. HIGH-Z TO VOL
A. VOH TO HIGH-Z
B. VOL TO HIGH-Z
Figure 1. Load Circuits for Data-Access Time Test
Figure 2. Load Circuits for Data-Hold TIme Test
____________________Pin Description
PIN 1 2 3-5 6 NAME VIN D0 D1-D3 WR/RDY FUNCTION Analog Input. Range is VREF- VIN VREF+. Three-State Data Output (LSB) Three-State Data Outputs Write Control Input/Ready Status Output* Mode Selection Input is internally pulled low with a 15A current source. MODE = 0 activates read mode MODE = 1 activates write-read mode* Read Input must be low to access data.* Interrupt Output goes low to indicate end of conversion.* Ground Lower limit of reference span. Sets the zero-code voltage. Range is VSS VREF- < VREF+. Upper limit to reference span. Sets the full-scale input voltage. Range is VREF- < VREF+ VDD. Chip-Select Input must be low for the device recognize WR or RD inputs. Three-State Data Outputs Three-State Data Output (MSB) Powerdown Input reduces supply current when low. Negative Supply. Unipolar: VSS = 0V, Bipolar: VSS = -3V. Positive Supply, +3V.
_______________Detailed Description
Converter Operation
The MAX152 uses a half-flash conversion technique (see Functional Diagram) in which two 4-bit flash ADC sections achieve an 8-bit result. Using 15 comparators, the flash ADC compares the unknown input voltage to the reference ladder and provides the upper 4 data bits. An internal digital-to-analog converter (DAC) uses the 4 most significant bits (MSBs) to generate the analog result from the first flash conversion and a residue voltage that is the difference between the unknown input and the DAC voltage. The residue is then compared again with the flash comparators to obtain the lower 4 data bits (LSBs). The MAX152 is characterized for operation between +3.0V and +3.6V. Conversion times decrease as the supply voltage increases. The supply current decreases rapidly with decreasing supply voltage. (See Typical Operating Characteristics.)
7
MODE
8 9 10 11
RD INT GND VREF-
12 13 14-16 17 18 19 20
VREF+ CS D4-D6 D7 PWRDN VSS VDD
Power-Down Mode
In burst-mode or low sample-rate applications, the MAX152 can be shut down between conversions, reducing supply current to microamp levels (see Typical Operating Characteristics). A logic low on the PWRDN pin shuts the device down, reducing supply current to typically 1A when powered from a single 3V supply. A logic high on PWRDN wakes up the MAX152. A new conversion can be started within 900ns of the PWRDN pin being driven high (this includes both the power-up delay and the track/hold acquisition time). If power-down mode is not required, connect PWRDN to VDD.
*See Digital Inferface Section. 6
_______________________________________________________________________________________
+3V, 8-Bit ADC with 1A Power-Down
Once the MAX152 is in power-down mode, lowest supply current is drawn with MODE low (RD mode) due to an internal pull-down resistor at this pin. In addition, for minimum current consumption, other digital inputs should remain high in power-down. Refer to the Reference section for information on reducing reference current during power-down.
Write-Read Mode (MODE = 1)
Figures 4 and 5 show the operating sequence for the write-read (WR-RD) mode. The comparator inputs track the analog input voltage for the duration of tP. The conversion is initiated by a falling edge of WR. When WR returns high, the 4 MSBs' flash result is latched into the output buffers and the 4 LSBs' conversion begins. INT goes low, indicating conversion end, and the lower 4 data bits are latched into the output buffers. The data is then accessible after RD goes low (see Timing Characteristics).
MAX152
___________________Digital Interface
The MAX152 has two basic interface modes set by the status of the MODE input pin. When MODE is low, the converter is in the RD mode; when MODE is high, the converter is set up for the WR-RD mode.
Read Mode (MODE = 0)
In RD mode, conversion control and data access are controlled by the RD input (Figure 3). The comparator inputs track the analog input voltage for the duration of tP. A conversion is initiated by driving RD low. With Ps that can be forced into a wait state, hold RD low until output data appears. The P starts the conversion, waits, and then reads data with a single read instruction. WR/RDY is configured as a status output (RDY) in RD mode, where it can drive the ready or wait input of a P. RDY is an open-collector output (with no internal pull-up) that goes low after the falling edge of CS and goes high at the end of the conversion. If not used, the WR/RDY pin can be left unconnected. The INT output goes low at the end of the conversion and returns high on the rising edge of CS or RD.
PWRDN CS WR tCSS RD tUP
tWR tCSH tRD tINTL tP tREAD2
INT D0-D7
VALID DATA tACC2 tDH
Figure 4. WR-RD Mode Timing (tRD > tINTL) (MODE = 1)
PWRDN PWRDN CS RD RDY tRDY INT tCRD D0-D7 tACCO tDH VALID DATA tUP tCSH WITH EXTERNAL PULL-UP tP tINTH INT CS WR tCSS RD
tUP
tCSH
tWR tRD
tP tREAD1 tRI tINTH VALID DATA tACC1 tCWR tDH
tCSS
Figure 3. RD Mode Timing (MODE = 0)
Figure 5. WR-RD Mode Timing (tRD < tINTL), Fastest Operating Mode (MODE = 1)
7
_______________________________________________________________________________________
+3V, 8-Bit ADC with 1A Power-Down MAX152
tWR WR tIHWR INT OLD DATA tINTL tP +3V 0.1F tID NEW DATA VIN+ VIN1V IN 10 GND
4.7F
MAX152 20 V DD 12 VREF+ 11 VREF-
D0-D7
Figure 6. Stand-Alone Mode Timing (CS = RD = 0) (MODE = 1)
Figure 7a. Power Supply as Reference
VIN+ VIN-
A minimum acquisition time (tP) is required from INT going low to the start of another conversion (WR going low). Options for reading data from the converter include the following:
10 20 GND VIN VDD VREF+
1
+3V
4.7 F
Using Internal Delay
The P waits for the INT output to go low before reading the data (Figure 4). INT goes low after the rising edge of WR, indicating that the conversion is complete and the result is available in the output latch. With CS low, data outputs D0-D7 can be accessed by pulling RD low. INT is then reset by the rising edge of CS or RD.
0.1 F 8 1 3
7
6 2
+2.5V 12 34.8k 3.01k
LM10
0.1 F VREF11
MAX152
4
Figure 7b. External Reference, +2.5V Full Scale
VIN+ 1V IN 10 GND +3V 0.1F 4.7F VIN1.2V 20 V MAX152 DD 12 11 VREF+ VREF-
Fastest Conversion: Reading Before Delay
An external method of controlling the conversion time is shown in Figure 5. The internally generated delay tINTL varies slightly with temperature and supply voltage, and can be overridden with RD to achieve the fastest conversion time. RD is brought low after the rising edge of WR, but before INT goes low. This completes the conversion and enables the output buffers (D0-D7) that contain the conversion result. INT also goes low after the falling edge of RD and is reset on the rising edge of RD or CS. The total conversion time is therefore: tCWR = tWR (600ns) + tRD (800ns) + tACC1 (400ns) = 1800ns.
*CURRENT PATH MUST STILL EXIST FROM VIN- TO GND.
0.1F
0.1F
Figure 7c. Input Not Referenced to GND
+3V VDD
MAX872
C1 2.2F PWRDN
+
MAX152 VREF+
VREFPWRDN N
Stand-Alone Operation
Besides the two standard WR-RD mode options, standalone operation can be achieved by connecting CS and RD low (Figure 6). A conversion is initiated by pulling WR low. Output data can be read by either edge of the next WR pulse.
MTD3055EL
Figure 7d. An N-channel MOSFET switches off the reference load during power-down.
8
_______________________________________________________________________________________
+3V, 8-Bit ADC with 1A Power-Down
____________Analog Considerations
Reference
Figures 7a-7c show some reference connections. VREF+ and VREF- inputs set the full-scale and zeroinput voltages of the ADC. The voltage at VREFdefines the input that produces an output code of all zeros, and the voltage at VREF+ defines the input that produces an output code of all ones. The internal resistance from VREF+ to VREF- may be as low as 1k, and current will flow through it even when the MAX152 is shut down. Figure 7d shows how an Nchannel MOSFET may be connected to VREF- to break this path during power-down. The FET should have an on resistance < 2 with a 3V gate drive. Although VREF+ is frequently connected to VDD, this circuit uses a low current, low-dropout, 2.5V voltage reference - the MAX872. Since the MAX872 cannot continuously furnish enough current for the reference resistance, this circuit is intended for applications where the MAX152 is normally in standby and is turned on in order to make measurements at intervals greater than 20s. The capacitor C1 connected to VREF+ is slowly charged by the MAX872 during the standby period and furnishes the reference current during the short measurement period. The 2.2F value of C1 is chosen so that its voltage drops by less than 1/2LSB during the conversion process. Larger capacitors reduce the error still further. Use ceramic or tantalum capacitors for C1. When VREF- is switched, as in Figure 7d, a new conversion can be initiated after waiting a time equal to the power-up delay (tUP) plus the turn-on time of the N-channel FET.
Input Current
Figure 8 shows the equivalent circuit of the converter input. When the conversion starts and WR is low, VIN is connected to sixteen 0.6pF capacitors. During this acquisition phase, the input capacitors charge to the input voltage through the resistance of the internal analog switches. In addition, about 12pF of stray capacitance must be charged. The input can be modeled as an equivalent RC network (Figure 9). As source impedance increases, the capacitors take longer to charge. The typical 22pF input capacitance allows source resistance as high as 2.2k without setup problems. For larger resistances, the acquisition time (tP) must be increased.
MAX152
MAX152
RIN VIN 1 VIN C RON
Figure 8. Equivalent Input Circuit
R VIN
1 VIN
4k
Bypassing
A 4.7F electrolytic in parallel with a 0.1F ceramic capacitor should be used to bypass V DD to GND. These capacitors should have minimal lead length. The reference inputs should be bypassed with 0.1F capacitors, as shown in Figures 7a-7c.
12pF
10pF
MAX152
Figure 9. RC Network Equivalent Input Model
_______________________________________________________________________________________
9
+3V, 8-Bit ADC with 1A Power-Down MAX152
Conversion Rate
The maximum sampling rate (fmax) for the MAX152 is achieved in the WR-RD mode (tRD < tINTL) and is calculated as follows: fmax = 1 t WR + t RD + t RI + t P
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal (in the frequency band above DC and below one-half the sample rate) to the fundamental itself. This is expressed as:
e.g. at TA = +25C, VDD = +3.0V : fmax = 1 600ns + 800ns + 300ns + 450ns
THD = 20 log
2 2 2 2 (V2 + V3 + V4 + L + VN ) V 1

where V1 is the fundamental RMS amplitude, and V2 to VN are the amplitudes of the 2nd through Nth harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range is the ratio of the fundamental RMS amplitude to the amplitude of the next largest spectral component (in the frequency band above DC and below one-half the sample rate). Usually the next largest spectral component occurs at some harmonic of the input frequency. However, if the ADC is exceptionally linear, it may occur only at a random peak in the ADC's noise floor. See "Signal to Noise Ratio" plot in Typical Operating Characteristics.
fmax = 465kHz where t WR = Write pulse width t RD = Delay between WR and RD pulses t RI = RD to INT delay t P = Delay time between conversons.
Signal-to-Noise Ratio and Effective Number of Bits
Signal-to-noise plus distortion ratio (SINAD) is the ratio of the fundamental input frequency's RMS amplitude to the RMS amplitude of all other ADC output signals. The output band is limited to frequencies above DC and below one-half the ADC sample rate. The theoretical minimum A/D noise is caused by quantization error, and results directly from the ADC's resolution: SNR = (6.02N + 1.76)dB, where N is the number of bits of resolution. Therefore, a perfect 8-bit ADC can do no better than 50dB. The FFT plot (Typical Operation Characteristics) shows the result of sampling a pure 30.27kHz sinusoid at a 400kHz rate. This FFT plot of the output shows the output level in various spectral bands. The effective resolution, or "effective number of bits," the ADC provides can be measured by transposing the equation that converts resolution to SNR: N = (SINAD 1.76)/6.02 (see Typical Operating Characteristics).
10
______________________________________________________________________________________
+3V, 8-Bit ADC with 1A Power-Down
___________________Chip Topography
MAX152
D0 VIN VDD VSS PWRDN D7 D6 0.104" 2.64mm D5 WR/RDY MODE CS D4
MAX152
D1 D2 D3
RD
INT
GND VREF0.098" 2.49mm
VREF+
TRANSISTOR COUNT: 1856 SUBSTRATE CONNECTED TO VDD
________________________________________________________Package Information
DIM A A1 A2 A3 B B1 C D D1 E E1 e eA eB L INCHES MAX MIN 0.200 - - 0.015 0.150 0.125 0.080 0.055 0.022 0.016 0.065 0.050 0.012 0.008 1.045 1.015 0.070 0.040 0.325 0.300 0.280 0.240 0.100 BSC 0.300 BSC 0.400 - 0.150 0.115 15 0 MILLIMETERS MIN MAX - 5.08 0.38 - 3.18 3.81 1.40 2.03 0.41 0.56 1.27 1.65 0.20 0.30 25.78 26.54 1.02 1.78 7.62 8.26 6.10 7.11 2.54 BSC 7.62 BSC - 10.16 2.92 3.81 0 15
21-333A
D1
E E1 A A2 D A3
A1 L e B B1
C eA eB
20-PIN PLASTIC DUAL-IN-LINE PACKAGE
11
______________________________________________________________________________________
+3V, 8-Bit ADC with 1A Power-Down MAX152
__________________________________________Package Information (continued)
DIM A A1 B C D E e H h L INCHES MAX MIN 0.104 0.093 0.012 0.004 0.019 0.014 0.013 0.009 0.512 0.496 0.299 0.291 0.050 BSC 0.419 0.394 0.030 0.010 0.050 0.016 8 0 MILLIMETERS MIN MAX 2.35 2.65 0.10 0.30 0.35 0.49 0.23 0.32 12.60 13.00 7.40 7.60 1.27 BSC 10.00 10.65 0.25 0.75 0.40 1.27 0 8
21-334A
E
H
D A
0.127mm 0.004in.
h x 45
e
B
A1
C
L
20-PIN PLASTIC SMALL-OUTLINE PACKAGE
12
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